Silicon-on-Insulator (SOI) Wafer

 

~$800M MILLION IN 2006 GROWING TO $1.2 BILLION BY 2009


 

Leading edge semiconductor devices are currently being manufactured at 65nm minimum feature sizes, but will continue to shrink and eventually reach sizes smaller than 25nm. As device sizes continue to shrink, a myriad of problems develop such as high leakage current, high power dissipation, transistor performance degradation and reduced reliability. These issues will demand new materials and material structures to solve them. One such solution is Silicon-on-Insulator or SOI, in which transistors are fabricated in a thin layer of silicon that is separated from the underlying silicon substrate by a layer of silicon oxide--a silicon-oxide-silicon sandwich. SOI structures have been widely acknowledged as a potential solution to many of the problems encountered as device sizes shrink below 65nm--in fact, to take advantage of the benefits, some semiconductor suppliers have already begun shipping in high volume, devices fabricated on SOI substrates.

One of the impediments to market adoption of SOI has been the expense and quality of SOI substrate wafers. Historically, SOI has been manufactured using bond and etch back techniques, high-energy ion implantation of oxygen (SIMOX), or more recently, thin film layer transfer. Except for SIMOX, these techniques can be termed lamination techniques (or layer transfer) and have been the subject of substantial research. SiGen has developed a suite of novel layer transfer lamination solutions that are covered by the family name SiGen NanoTec. SiGen's layer transfer (LT) technology, which produces SOI substrates of high quality and low cost, enables high volume manufacturing and more rapid adoption of SOI. In addition, the SiGen NanoTec layer transfer process is a "clean" process in that it eliminates wafer sawing, thinning and grinding to achieve high quality thin films. The Company believes that its revolutionary SiGen NanoTec technology will enable it to become the dominant supplier of SOI and other substrate engineering IP to the Semiconductor industry.

 

 

 

 

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