Silicon-on-Insulator (SOI) Wafer
~$800M MILLION IN 2006 GROWING TO $1.2 BILLION BY 2009
Leading edge semiconductor devices are currently being manufactured at 65nm minimum feature sizes, but will continue to shrink and eventually reach sizes smaller than 25nm. As device sizes continue to shrink, a myriad of problems develop such as high leakage current, high power dissipation, transistor performance degradation and reduced reliability. These issues will demand new materials and material structures to solve them. One such solution is Silicon-on-Insulator or SOI, in which transistors are fabricated in a thin layer of silicon that is separated from the underlying silicon substrate by a layer of silicon oxide--a silicon-oxide-silicon sandwich. SOI structures have been widely acknowledged as a potential solution to many of the problems encountered as device sizes shrink below 65nm--in fact, to take advantage of the benefits, some semiconductor suppliers have already begun shipping in high volume, devices fabricated on SOI substrates.